Sophisticated design of low power high speed full adder by using SR-CPL and Transmission Gate logic. International Journal of Advance Engineering and Research Development (IJAERD), [S. l.], v. 2, n. 3, p. 137–142, 2015. Disponível em: https://ijaerd.org/index.php/IJAERD/article/view/543. Acesso em: 28 jul. 2025.