HARESH P. PATANI; NILESH D. PATEL. Characterization and Simulation of Self Cascode CMOS Current Mirror Circuit using 0.18μm Technology. International Journal of Advance Engineering and Research Development (IJAERD), [S. l.], v. 2, n. 4, p. 626–629, 2015. Disponível em: https://ijaerd.org/index.php/IJAERD/article/view/730. Acesso em: 7 jul. 2025.