Paper Details

The need for ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the useof dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of thedynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designerscan obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamiccomparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of aconventional double tail comparator is modified for low-power and fast operation even in small supply voltages. Withoutcomplicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, whichresults in remarkably reduced delay time. Post-layout simulation results in a 32nm CMOS technology confirm the analysisresults. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantlyreduced. The maximum clock frequency of the proposed comparator can be increased to 2G and 1.1 GHz at supply voltagesof 1.2 V and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is7.8 mV at 1.2 V supply

Ms.Nikhila.Paruchur, Smt Maya S Pati, Dr K Ramesh Babu, “Design of a Low-Voltage, Power & Double Tail Comparator Using CNTFET”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 9, pp. 113-124, September 2014.