Paper Details

The recently proposed dual mode logic (DML) gates family enables a very high level of power delayoptimization flexibility at the gate level. In this paper, this flexibility is utilized to improve power efficiency andperformance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates thedesign's critical paths (CPs) and operates these paths in the boosted performance mode is proposed. The noncritical pathsare operated in the low energy DML mode, which does not affect the performance of the design, but allows significantpower consumption reduction. The proposed work is analyzed on 4bit carry skip adder, carry propagate adder, ripplecarry adder and carry select adder. Simulations, carried out in a standard 180 nm dig ital CMOS process at differentvoltage levels VDD from 1v to 1.8v, show that the proposed approach allows performance improvement along withreduction of energy consumption, as compared with a standard CMOS implementation.

Anantha Reddy K, T. Vasudeva Reddy, “Design and Verification of Dual Mode Logic (DML) for Power Efficient and High Performance”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 12, pp. 1-8, December 2014.