Paper Details

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages inand all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analogsignal saver long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog testvoltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locallyconverts the test voltage to a skew between a pair of sub sampled signals, thus giving rise to as many sub sampled signalpairs as the number of nodes. To measure a certain analog voltage, the corresponding sub sampled signal pair is fed to adelay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC130-nm CMOS process .Sub-mill volt accuracy for static signals is demonstrated for measurement time of a few seconds, andan effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.

G.USHA RANI, L.S.DEVARAJ, “TIME-BASED ALL-DIGITAL TECHNIQUE FOR ANALOGBUILT-IN SELFTEST”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 5, pp. 1189-1197, May 2015.