Area Efficient and High Speed ALU Using 64 Bit Modified Square Root Carry Select Adder
| Author(s) | : | N. Pranav, P.Anil Kumar |
| Institution | : | M.Tech, S.V. Engineering College for Women |
| Published In | : | Vol. 4, Issue 7 — July 2017 |
| Page No. | : | 638-342 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
In digital computer, an Arithmetic logic unit (ALU) is a crucial combinational circuit that executes arithmeticand logical functions. Parallel adder in ALU plays an essential role, however the speed of addition is limited by the timerequired to transmit a carry through the adder. For area-efficient and high performance computer applications, 64-Bitmodified Square Root Carry Select Adder (SQRT CSLA) based ALU is proposed. This paper delivers the design andimplementation of 64-Bit modified SQRT CSLA based ALU. Compares it with the regular SQRT CSLA in terms of areaand speed. The design entry can be described in Verilog .For simulate and synthesize use Altera QUARTUS-II 9.1.Theresults analysis shows that the proposed SQRT CSLA structure is better than the regular SQRT CSLA
N. Pranav, P.Anil Kumar, “Area Efficient and High Speed ALU Using 64 Bit Modified Square Root Carry Select Adder”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 7, pp. 638-342, July 2017.
