Design and Implementation of Low Power High-Speed 16-bit Arithmetic Units using different Multipliers in Cadence Virtuoso using 45nm technology
| Author(s) | : | J.SREEJA, RAJESHWARI SOMA |
| Institution | : | Student, CVR College Of Engineering, Hyderabad |
| Published In | : | Vol. 4, Issue 9 — September 2017 |
| Page No. | : | 90-95 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
A low power high-speed four Arithmetic Units are designed using different multipliers, each multiplier ineach Arithmetic Unit. This project helps to choose a low power high-speed Arithmetic Unit in designing of differentsystems.AU stands for Arithmetic Unit, which is the main functional unit in most digital and high- performance systemsThe performance of Arithmetic Unit mainly depends on the performance of multiplier. The speed and area of themultiplier to be optimized is a major design issue. To determine the best solution for this problem is by comparing AUwith different multipliers. Four different types of multipliers, Array, Wallace, Baugh-Wooley, Vedic multipliers weredesigned using half adders and full adders. Power and delay of Arithmetic Unit with different multipliers are compared.The working of AU using different multipliers helps to frame a better system with less power consumption and highspeed. The entire design is done using CADENCE Tool with a power supply of 1V in GPDK 45nm technology.
J.SREEJA, RAJESHWARI SOMA, “Design and Implementation of Low Power High-Speed 16-bit Arithmetic Units using different Multipliers in Cadence Virtuoso using 45nm technology”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 9, pp. 90-95, September 2017.








