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📢 Call for Papers — Volume 13, Issue 7 (July 2026) | Submission Deadline: July 31, 2026 | Rapid peer review: 2–3 days | Impact Factor: 7.37 (SJIF 2026)

Paper Details

📄 IJAERD-OJS-4341

Multicoding Techniqe to Reduce Power Dissipation in VLSI:A Review

Author(s):Gajanan S. Girhe, S. S. Thakre
Institution:Electronics and Telecommunication Department, GCOE,Amravati, Amravati, India
Published In:Vol. 4, Issue 12 — December 2017
Page No.:16-20
Domain:Engineering
Type:Research Paper
ISSN (Online):2348-4470
ISSN (Print):2348-6406
Abstract

CMOS VLSI circuits having profuse number of gates are interconnected with every part to perform thelogical manipulation by input signal. The input signal changes from 0 to 1 or vice-versa, it will change and spread viathe circuit and results in power disappearing in the circuit. The charging and discharging of parasitic capacitance ismain cause of the power dissipation in the circuit, this is dynamic power dissipation in CMOS circuit. Deep Submicron(DSM) is the one of technology to reduce the area of system. The focus is to reduce the area of CMOS VLSI circuit. Thereare several methods for the reduction of dynamic power dissipation through energy transition in data buses. Among thema novel Multi coding technique for reducing dynamic power dissipation is proposed by reduction in switching activity ofself transitions. In this method, the applied input data is coded in five different ways and the coding resulting inmaximum reduction in transition activity is selected. Through this coding scheme the average transition activity isreduced. The coding technique gives better results for longer bus width.

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🕮 How to Cite

Gajanan S. Girhe, S. S. Thakre, “Multicoding Techniqe to Reduce Power Dissipation in VLSI:A Review”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 12, pp. 16-20, December 2017.

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Vol. 13 | Issue 7
July 2026