Paper Details

In pulse triggered flip flop design there is the delay discrepancy in latching data “1” and “0”, the designmanages to shorten the longer delay by feeding the input signal directly to an internal node of the latch design to speedup the data transition. But Half of the injected energy from the power supply is dissipated in the PMOS network whileonly one half is delivered to the output node. (0 to VDD transition) Energy stored in the load capacitance is dissipated inthe NMOS network (VDD to 0 transition). There are many methods to reduce power dissipation. Of all these methodsAdiabatic logic is the efficient one to reduce power dissipation. In this document, the pulse triggered flip-flops areimplemented using Positive Feedback Adiabatic Logic. By using the positive feedback adiabatic logic (PFAL) the powerconsumption can be reduced to an extent.The design was simulated was by using Mentor Graphics tool 180nmTechnology,by using this the power will be reduced 13.034mw to 3.0372mw.

G.Srikaladevi, K.Sree Lakshmi, “PULSE TRIGGERED FLIP FLOP DESIGN BY USING ADIABATIC LOGIC”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 10, pp. 103-108, October 2015.