📄 IJAERD-OJS-5716
Simulation of Phase Locked Loop Circuit in Non-Linear Load
| Author(s) | : | Rana Urvesh Rameshbhai |
| Institution | : | Assistant Professor Electrical Engineering, Parul Institute of Technology, Vadodara, India |
| Published In | : | Vol. 2, Issue 13 — January 2015 |
| Page No. | : | - |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Abstract
Nonlinear load produces the harmonics in the supply system and deteriorate voltage and current wave shape. Thisdistortion can beminimized by use of PLL.This paper presents the effective solution to reduce harmonics by using phase locked loop (PLL). This papercontains simulation of PLL in three phase system. Simulation results are also shown in the paper.
🕮 How to Cite
Rana Urvesh Rameshbhai, “Simulation of Phase Locked Loop Circuit in Non-Linear Load”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 13, pp. -, January 2015.
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