Design of High speed fixed and reconfigurable FIR filter for speech signal processing

Abstract

Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant
multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration
does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of
realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters
for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration
of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A
generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based
architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the
MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves
significantly less area-delay than the existing block implementation of direct-form structure for medium or large filter
lengths, while for the short-length filters For the same filter length and the same block size, the proposed structure involves
less area and delay that of the existing direct-form block FIR structure. All the synthesis and simulation results of the
Proposed High performance FIR Filters are performed on Xilinx ISE 14.7 using Verilog HDL.