Comparative Analysis of Full Adders Using different MOS Technologies

Authors

  • Yadwinder Kaur
  • Sonia Malhotra Department of ECE, BBSBEC Fatehgarh Sahib

Keywords:

CMOS Transmission Gate (TG), Pass-Transistor Logic (PTL), Complementary Pass transistor Logic (CPL),), full adder Power, Delay, Channel Length.

Abstract

With the development in the fabrication techniques the numbers of the transistors on a chip are increasing at much
faster rate, results in the very large scale integration. This paper discusses the comparative analysis of full adder circuits in
terms of higher speed and size. All these three parameters depend upon each other and trade-off exists within these. A 4bit
adder is designed using different MOS technologies These Techniques include CMOS technology designing with transmission
gate and designing adder with combination of Complimentary Pass Logic and Transmission gate & simulated using 180nm,
130nm & 100nm technology files

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Published

2014-08-25

How to Cite

Yadwinder Kaur, & Sonia Malhotra. (2014). Comparative Analysis of Full Adders Using different MOS Technologies. International Journal of Advance Engineering and Research Development (IJAERD), 1(8), 145–149. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/204

Issue

Vol. 1 No. 8 (2014): Volume 1 Issue 8 (August-2014)

Section

Articles