Design of a Low-Voltage, Power & Double Tail Comparator Using CNTFET
Keywords:
ultra low voltage power, double tail CMOS, UDSM etcAbstract
The need for ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the use
of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the
dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers
can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic
comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a
conventional double tail comparator is modified for low-power and fast operation even in small supply voltages. Without
complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which
results in remarkably reduced delay time. Post-layout simulation results in a 32nm CMOS technology confirm the analysis
results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly
reduced. The maximum clock frequency of the proposed comparator can be increased to 2G and 1.1 GHz at supply voltages
of 1.2 V and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is
7.8 mV at 1.2 V supply