Area Efficient and High Speed ALU Using 64 Bit Modified Square Root Carry Select Adder
Keywords:
-Abstract
In digital computer, an Arithmetic logic unit (ALU) is a crucial combinational circuit that executes arithmetic
and logical functions. Parallel adder in ALU plays an essential role, however the speed of addition is limited by the time
required to transmit a carry through the adder. For area-efficient and high performance computer applications, 64-Bit
modified Square Root Carry Select Adder (SQRT CSLA) based ALU is proposed. This paper delivers the design and
implementation of 64-Bit modified SQRT CSLA based ALU. Compares it with the regular SQRT CSLA in terms of area
and speed. The design entry can be described in Verilog .For simulate and synthesize use Altera QUARTUS-II 9.1.The
results analysis shows that the proposed SQRT CSLA structure is better than the regular SQRT CSLA
