COMPARATIVE PERFORMANCE ANALYSIS OF OPTIMIZED POWER AND AREA FOR FULL ADDER USING GDI CELL

Authors

  • NANDEESH M Assistant Professor Dept of ECE BGSIT BG Nagar
  • PRADEEP N T Students Dept of ECE BGSIT BG Nagar.
  • SAGAR H D Students Dept of ECE BGSIT BG Nagar
  • SUNIL H S Students Dept of ECE BGSIT BG Nagar
  • VINAY KUMAR B S Students Dept of ECE BGSIT BG Nagar

Keywords:

GDI technique, Ripple carry adder, CMOS and CPL

Abstract

This paper presents a high drivability of full adder with less area and power consumption. This GDI based
full adder is implemented by using both gate diffusion input (GDI) technique and pass transistor logic that leads to be a
reduced area and power.. The comparison has been done between existing systems like CMOS, CPL, 14T full adder and
proposed full adder. All full adders are designed with 0.18um in tanner schematic and simulations are done in T-Spice.
Tool .By Using this full adder we have designed the ripple carry adder and carry skip adder which is compared with all
existing systems and finally concluded that our proposed method is showing better results in terms of area and power
hence we can say our method is efficient in area and power consumption.

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Published

2018-05-25

How to Cite

NANDEESH M, PRADEEP N T, SAGAR H D, SUNIL H S, & VINAY KUMAR B S. (2018). COMPARATIVE PERFORMANCE ANALYSIS OF OPTIMIZED POWER AND AREA FOR FULL ADDER USING GDI CELL. International Journal of Advance Engineering and Research Development (IJAERD), 5(5), 81–89. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/3398

Issue

Vol. 5 No. 5 (2018): Volume 5 Issue 5 May 2018

Section

Articles

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