IMPLEMENTATION OF 2GBPS CLOCK AND DATA RECOVERY CIRCUIT USING PLL WITH HIGH JITTER TOLERANCE

Authors

  • Dr. Suma M.S. Electronics and communication (VLSI Design), R.V.COLLEGE OF ENGG. AND TECH, BANGALORE
  • Krishna Basidoni Electronics and communication (VLSI Design), R.V.COLLEGE OF ENGG. AND TECH, BANGALORE

Keywords:

s-Phase Locked Loop (PLL), Phase Detector (PD), Charge Pump (CP), Loop Filter, Voltage Controlled Oscillator (VCO),Frequency Divider, Lock -in range, Lock time.

Abstract

The data integrity that the SerDes offers is predominantly due to the Clock and Data Recovery Circuit (CDR)
employed within the design. The CDR takes the incoming data and generates a clock using the data specs which can then be
used by the deserializer to sample the data accurately. This paper looks into the basic principles of operation of Phase
Locked Loops, Clock and Data recovery circuits and their building blocks for a 2 Gbps SerDes link with high jitter tolerance.
Implementation of differential mode VCO with low gain to reduce the jitter. It summarizes the challenges in design and also
presents a Cadence approach to the circuit design in 180 nm CMOS technology.

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Published

2015-02-25

How to Cite

Dr. Suma M.S., & Krishna Basidoni. (2015). IMPLEMENTATION OF 2GBPS CLOCK AND DATA RECOVERY CIRCUIT USING PLL WITH HIGH JITTER TOLERANCE. International Journal of Advance Engineering and Research Development (IJAERD), 2(2), 56–63. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/487

Issue

Vol. 2 No. 2 (2015): Volume 2 Issue 2, February 2015

Section

Articles