HIGH SPEED MULTIOPERAND REDUNDANT ADDERS USING COMPRESSOR TREES

Authors

  • NALLAPETA.ANIL Pg Scholar, Vlsi System Design , Intellectual Institute Of Technology, Ap, India
  • W.YASMEEN Assistant Professor, Intellectual Institute Of Technology, Ap, India

Keywords:

Computer arithmetic, multioperand addition, redundant representation, carry-save adders

Abstract

Here we present different approaches to the efficient Implementation of generic carry-save compressor trees on
FPGAs. They present a fast critical path, independent of bit width, with practically no area overhead compared to CPA trees.
Along with the classic carry-save compressor tree, here we present a novel linear array structure, which efficiently uses the
fast carry-chain resources. This approach is defined in a parameterizable HDL code based on CPAs, which makes it
compatible with any FPGA family or vendor.

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Published

2015-03-25

How to Cite

NALLAPETA.ANIL, & W.YASMEEN. (2015). HIGH SPEED MULTIOPERAND REDUNDANT ADDERS USING COMPRESSOR TREES. International Journal of Advance Engineering and Research Development (IJAERD), 2(3), 63–67. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/515

Issue

Vol. 2 No. 3 (2015): Volume 2 Issue 3, March 2015

Section

Articles