HIGH SPEED MULTIOPERAND REDUNDANT ADDERS USING COMPRESSOR TREES

Abstract

Here we present different approaches to the efficient Implementation of generic carry-save compressor trees on
FPGAs. They present a fast critical path, independent of bit width, with practically no area overhead compared to CPA trees.
Along with the classic carry-save compressor tree, here we present a novel linear array structure, which efficiently uses the
fast carry-chain resources. This approach is defined in a parameterizable HDL code based on CPAs, which makes it
compatible with any FPGA family or vendor.