A NOVEL APPROACH FOR VERIFICATION OF RISC-V PROCESSOR

Authors

  • Ramanpreet Virdi Department of Electrical, Electronics & Communication Engineering, The NorthCap University, Gurgaon, Haryana, India
  • Neeraj Kr. Shukla Department of Electrical, Electronics & Communication Engineering, The NorthCap University, Gurgaon, Haryana, India

Keywords:

ISA, Risc-V, Verilator, Vlang.

Abstract

The CPU is a standout amongst the most significant segments of our PCs, dependable of performing
essential figuring, legitimate correlations and moving information around. These straightforward errands are the
building squares of any more unpredictable operation, and make running our frameworks and projects conceivable. This
paper shows the better approach to verify the RISC-V (Reduced Instruction Set Architecture) processor which can incite
minimal effort as the open source Verification Language (Vlang).

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Published

2022-08-23

How to Cite

Ramanpreet Virdi, & Neeraj Kr. Shukla. (2022). A NOVEL APPROACH FOR VERIFICATION OF RISC-V PROCESSOR. International Journal of Advance Engineering and Research Development (IJAERD), 5(13), -. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/6286

Issue

Vol. 5 No. 13 (2018): ETIECE-2017 (Emerging Trends and Innovations in Electronics and Communication Engineering)

Section

Articles