Area and Power Efficient Layout Design of Inverter

Authors

  • Mehmood-ul –Hasan Department of Electronics & Communication Engineering,Baba Ghulam Shah Badshah University, Rajouri
  • Ghulam Ahmad Raza Department of Electronics & Communication Engineering,Siwan Engineering & Technical Institute, Siwan

Keywords:

CMOS inverter; Dynamic Power; NMOS; PMOS; Static Power; VLSI

Abstract

In recent years, the demand for low power devices has grown significantly. This growth is mainly due to the fast
growth of battery-operated semiconductor devices such as cell phone, tablets, laptop etc. Reducing power consumption and
surface area in integrated circuit is an important factor for both portable and desktop applications. In this paper an inverter
and its layout have been designed using PMOS and NMOS transistors. The result has been compared in terms of power
consumption and surface area. The simulated results show that semi-custom layout of an inverter consumes 52.5% more
power and 35.9% more surface area than the full custom layout of inverter

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Published

2022-08-23

How to Cite

Mehmood-ul –Hasan, & Ghulam Ahmad Raza. (2022). Area and Power Efficient Layout Design of Inverter. International Journal of Advance Engineering and Research Development (IJAERD), 5(13), -. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/6289

Issue

Vol. 5 No. 13 (2018): ETIECE-2017 (Emerging Trends and Innovations in Electronics and Communication Engineering)

Section

Articles