NOVEL ENERGY EFFICIENT CARRY SKIP ADDER BASED ON DUAL MODE LOGIC DESIGN

Abstract

The dual mode logic (DML) gates family proposed here empowers a very high level of energy-delay
optimization flexibility at the very gate level. In this paper, this adaptability is utilized to enhance energy efficiency and
performance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates the
design's critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths operate
in the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumption
reduction. The proposed approach is analyzed on a 128 bit carry skip adder.