Review on “FPGA based high speed, low power matrix multiplier using Urdva Triyagbhyam algorithm”
| Author(s) | : | Miss Pranjali J. Rathod, Prof. S. S. Mungona |
| Institution | : | Electronics and telecommunication engineering, sipna college of engineering and technology |
| Published In | : | Vol. 3, Issue 11 — November 2016 |
| Page No. | : | 304-309 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Matrix multiplication is a computation intensive operation and plays an important role in many scientificand engineering applications such as image processing, discrete signal processing. This paper presents architecture forthe multiplication of two matrices using Field Programmable Gate Array (FPGA).This paper presents unsigned two 3x3High-Speed matrix multiplier The hierarchical structuring has been used to optimize for multipliers using “UrdhavaTrigyagbhyam” sutra (vertically and crosswise)which is one of the sutra for Vedic mathematics. Each element of matrixis represented by 4-bit,output is of 8 bit. The coding has been done using VHDL and synthesized using Altera Quartus II.A concept of design is hierarchical structuring; This gives less computation time for calculating the multiplication result.We will synthesized the proposed designs and the existing design using Altera Quartus II tools. The proposed structureconsumes less energy.
Miss Pranjali J. Rathod, Prof. S. S. Mungona, “Review on “FPGA based high speed, low power matrix multiplier using Urdva Triyagbhyam algorithm””, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 3, Issue 11, pp. 304-309, November 2016.
