Improved Data Efficiency of Programmable Arbiter Based On-Chip Permutation Network for MPSOC

Abstract

This paper presents the design of a novel OCP network to support guaranteed traffic permutation in
multiprocessor SOC applications. The proposed network employs a pipelined circuit-switching approach combined with a
dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path
arrangement for arbitrary traffic permutations. The existing system having only fixed priority logic scheme for dynamic path
set up .In this paper we proposed a new PAB based priority logic to rectify the drawbacks in previous arbiter system in
proposed OCP network. The PAB contains F-Priority, RR-Priority, D-Priority logics. This circuit-switching approach offers
a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple net-works. The proposed on
chip network improves the efficiency. Finally implemented the design using Xilinx ISE 12.1 software on FPGA Spartan 3E
family kit, NEXYS 2 board and showed the synthesis result and power result. The Proposed system OCP network with PAB
improves the power, delay and improves the data efficiency.