SYSTEMATIC ERROR CODES IMPLIMENTATION FOR MATCHED DATA ENCODED

Abstract

In current scenario, there are situations in a computing system where incoming information needs to be
compared with a piece of stored data to locate the matching entry, e.g., cache tag array lookup and translation look-aside
buffer matching. In this paper, a new architecture to reduce complexity and latency for matching the data protected with an
error-correcting code (ECC).It is based on the fact that the code word of an ECC generated by encoding is usually
represented in a systematic form, and it consists of the raw data and the parity informa tion. The proposed architecture
parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in
addition, a modified butterfly formed weight accumulator (BWA) is proposed for the effic ient computation of the Hamming
distance. The proposed architecture examines whether the incoming data matches the sto red data if a certain number of
erroneous bits are correct.