SIMULATION & ANALYSIS OF WIDEBAND AND LOW POWER CMOS ANALOG MULTIPLIER IN DEEP SUBMICRON TECHNOLOGY

Abstract

In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on
combiner circuit and subtractor circuit, where subtractor circuit is used for input block and
combiner circuit is act as nonlinear cancellation path. Simulated results using Eldo spice in
Mentor Graphics Tools for a standard TSMC 180nm CMOS technology and power supply
VDD is taken 1.5V. The main performances of the multiplier including bandwidth, power
dissipation, and gain are improved.