Characterization and Simulation of Self Cascode CMOS Current Mirror Circuit using 0.18μm Technology

Authors

  • Haresh P. Patani PG Student, Electronics & Communication Department LCIT-Bhandu College, GTU, Gujarat, India
  • Nilesh D. Patel Assistant Professor, Electronics & Communication Department LCIT-Bhandu College, Mahesana, Gujarat, India

Keywords:

Current mirror, cascode current mirror, low voltage analog circuit, analog and mix VLSI design.

Abstract

Current mirror is the core structure for almost all analog and mixed signal VLSI design circuits determine
the performance of analog structures, which largely depends on their characteristics. In this paper the current mirror
circuits presented, which having low voltage and high output resistance structure has been proposed. The performance
of self-cascade CMOS current mirror is optimized with high output impedance and can operate at 1 V or below. The
proposed circuit has an input current range of operation is 10μA.To support the analysis, circuit is simulated using Eldospice, IC Station and Design Architect(Mentor Graphics).To carry out the simulation, TSMC 0.18μm technology is used

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Published

2015-04-25

How to Cite

Haresh P. Patani, & Nilesh D. Patel. (2015). Characterization and Simulation of Self Cascode CMOS Current Mirror Circuit using 0.18μm Technology. International Journal of Advance Engineering and Research Development (IJAERD), 2(4), 626–629. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/730

Issue

Vol. 2 No. 4 (2015): Volume 2 Issue 4, April 2015

Section

Articles