High performance dual output CMOS Realization of the Third Generation Current Conveyor (CCIII)

Authors

  • Prachi Parikh PG Student, Gujarat Technology University, Electronics and Communication, LCIT-Bhandu, Mehsana, Gujarat, India prachiparikh1989@gmail.com
  • Gireeja Amin Assistant Professor. Electronics and Communication, LCIT-Bhandu, Mehsana, Gujarat, India, gireeja.amin@lcit.org

Keywords:

CMOS Circuits, CCIII, SPICE

Abstract

In this paper a new CMOS high performance dual-output realization of the third generation
current conveyor (CCIII) is presented. The presented CCIIl provides good linearity, high output
impedance at port Z and excellent input/output current gain. SPICE simulation results using TSMC
0.18μm and Generic 0.09μm CMOS process parameters in Mentor Graphics are given.

Downloads

Published

2014-05-25

How to Cite

Prachi Parikh, & Gireeja Amin. (2014). High performance dual output CMOS Realization of the Third Generation Current Conveyor (CCIII). International Journal of Advance Engineering and Research Development (IJAERD), 1(5), 648–654. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/122

Issue

Vol. 1 No. 5 (2014): Volume 1 Issue 5 (May-2014)

Section

Articles