IMPLEMENTATION OF 24 BIT HIGH SPEED FLOATING POINT VEDIC MULTIPLIER
Keywords:
Fast Fourier Transform, Urdhava-Tiryakbhyam, Vedic Mathematics, Libero Ide V9.1, ModelsimAbstract
The computational complexity of various data processing applications is vastly reduced when signals are
represented in the frequency domain. In launch vehicle systems, FFT is required for telemetry data processing
applications. Since the systems work in real time, a fast and efficient computation of the FFT is called for. FFT
multiplication deals with Floating point numbers. Vedic mathematics is an ancient multiplication procedure which is
widely used in every field that requires computations. The Urdhva Tiryakbhyam sutra is used because it will reduce
computation time than conventional multipliers. Digital Signal Processing applications essentially require the
multiplication of binary floating point numbers. For IEEE754 floating point multiplier implementation, Vedic
Multiplication Method is used. The ease of multiplication of Mantissa part is done by Urdhva Tiryakbhyam method. This
paper deals with the 24 bit floating point implementation using IEEE754 multiplication based on vedic mathematics and
compare the result with conventional multi plier. Design and HDL coding was carried out using Verilog using the Libero
IdeV9.1 project environment, natively used for the Actel Pro-Asic devices. The code synthesis was done using Synplify
and simulation stage was done using Modelsim
