Review of Low Powered High Speed and Area Efficient Full Adders

Authors

  • R.Senthil Ganesh Assistant Professor, Electronics and Communication Engineering, Info Institute of Engineering, Tamilnadu
  • K.Hemamalini Assistant Professor, Electronics and Communication Engineering, Info Institute of Engineering, Tamilnadu
  • V.Indhu UG Scholar, Electronics and Communication Engineering, Info Institute of Engineering,Tamilnadu
  • S. Kamala Prabha UG Scholar, Electronics and Communication Engineering, Info Institute of Engineering,Tamilnadu

Keywords:

PDP, Full Adders, GDI, SERF

Abstract

Adders are the basic building block of all digital systems. Addition is the basic operation performed in all
arithmetic operations. Addition is the important operation in arithmetic operation because all the other operations are done
using addition. Developing technology is in need of the high performance and low power digital circuits. In order to achieve
that we should increase the performance and reduce the power consumption of full adder. Here the comparative analysis of
speed, average power consumption, static power dissipation, Power Delay Product [PDP] of various full adders such as full
adder 9A, full adder 9B, 10T full adder, 10T adder 1,13A full adder, Gate Diffusion Input [GDI], modified full adder 9A,
modified full adder 9B, Static Energy Recovery Full Adder [SERF] and the conventional 28T full adder was performed.

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Published

2018-02-25

How to Cite

R.Senthil Ganesh, K.Hemamalini, V.Indhu, & S. Kamala Prabha. (2018). Review of Low Powered High Speed and Area Efficient Full Adders. International Journal of Advance Engineering and Research Development (IJAERD), 5(2), 770–778. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/2488

Issue

Vol. 5 No. 2 (2018): Volume 5 Issue 2 February 2018

Section

Articles

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