REA OPTIMIZATION AND PERFORMANCE IMPROVEMENT OF CARRY SPECULATIVE ADDITION BY MODIFYING BLOCK ADDER AND ERROR CORRECTION CIRCUIT
Keywords:
Full adder, speculation, critical path delay, variable latency, error detection, error recoveryAbstract
This paper proposes carry speculative addition using modified error correction, block adder design to reduce
critical path delay there by reducing area and power consumption. The modified error correction block and block adder
possesses less number of gates compared with existing circuit. The complete proposed Carry Speculative Addition using
modified error correction and block adder with a data latching circuit to get continuous data into circuit architecture is
implemented using Verilog HDL and the design is simulated using Xilinx ISE and vivado 2016.4,artix 7 family device
XC7A100TCSG324-1.