Performance Efficient MDC based Pipelined FFT Processor for MIMO-OFDM

Abstract

This paper presents a pipelined radix-2 FFT processor, which is efficient in terms of its delay, power and
area, to process two independent data streams concurrently. This processor generates outputs in natural order without
using bit reversal circuits. The shift registers, which are used to delay the data samples, perform bit reversal operation
also. This FFT uses two N/2-point multipath delay commutator FFT architectures to process even and odd samples of
two data streams separately. This FFT processor uses Kogge-Stone adders and Dadda multipliers in its butterfly
processing units. The Kogge-stone adder is a parallel prefix form of carry look ahead adder and widely used high
performance adder in the industries of the present day. Since the adder used generates the carry signal in O(log2n) time,
it is widely considered to be the fastest adder design possible. The Dadda multiplier is based on row reduction of partial
products by compressing columns using less full adders and half adders compared to the conventional multipliers. Thus,
the Dadda multiplier’s speed is more and takes less hardware. Therefore, by using the Kogge-Stone adders and Dadda
multipliers in butterfly processing units, the proposed FFT processor has less delay, less area and consumes less power
compared to the conventional FFT architectures.