Design of DPLL and Implementation of BIST to Evaluate its Characteristics

Abstract

All digital systems need to synchronize between Integrated Circuits and functional blocks, mainly to
progress digital systems operations for excellence in performance. Future processors need to work with different ICs and
IPs, whose operating speed is different; there is requirement for high speed clocks. This has to be done by just using the
low frequency on board clock. To generate the on-chip clocks to have well-timed, Phase locked-loops (PLLs) are used.
But designing a fully digital PLL is needed because all the designs are digital and analog component will need more
power and will reduce efficiency. Most of the traditional PLL are monolithic design with other circuits. The proposed
DPLL is just based on counters, dividers and digital phase lock detectors which are easy to fabricate when compared to
analog component and can be integrated in any system easily. It can generate wide range of frequencies and has in built
BIST to test the operation of PLL and to determine characteristics like lock time, jitter and duty cycle. The experimental
results of DPLL with waveforms are shown for 50 MHz reference clock signal to generate 200 MHz clock DPLL. BIST
for the PLL is implemented using TESSENT TOOL.