Floating-point butterfly architecture based on redundant number system and Fused-Dot-Product-Add unit

Abstract

The Fast Fourier transforms (FFT) plays a major role in ruling the performance of many communication
systems. The butterfly unit is the major building block of FFT architectures which mainly consists of addition and
multiplication operations over complex numbers. The number representation plays an important role in enhancing the
speed of any digital system. The strings of digits can be represented using floating-point (FP) arithmetic or fixed-point to
design butterfly unit. The FP arithmetic provides a wide dynamic range by reducing the design constraints like scaling
and overflow/underflow, but it has low performance issues in terms of speed when compared to fixed-point
representation. The fused-dot-product-add (FDPA) unit based on binary sign digit representation (BSD) is used to
increase the speed of FP butterfly architecture; it is used to compute AB±CD±E. The FDPA unit consists of FP BSD
multiplier and FP BSD three-operand-adder units that use a BSD carry-limit adder. FP three-operand adder using
comparator is proposed to reduce the area and delay of the FDPA unit and a new BSD adder is further proposed to
increase the speed of the existing architectures. The simulations of the architectures in this paper are done by using
Xilinx software for efficient result