LOW POWER MULTIPLIER USING BYPASSINGZERO ARCHITECTURE

Authors

  • Nishant Govindrao Pandharpurka Deparment of SENSE, VITUniversity
  • Antriksh sharma Department of SENSE, VIT University

Keywords:

synchronous low power ripple counter, Bypass and Feeder register, Bypassing zero procedure, pmos array

Abstract

This paper presents the implementation of multipliers with Bypassing the Zero architecture based on shift and
add multiplication. Using this architecture a considerable amount of switching power can be reduced as compared to
conventional shift and add multipliers. For this purpose, synchronous ring counter is used instead of conventional binary
counter. Note that Shifting of only most significant partial products has been done. Simulation results shows that this
architecture lowers switching cases and lowers power consumption up to 30%-40%.

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Published

2015-02-25

How to Cite

Nishant Govindrao Pandharpurka, & Antriksh sharma. (2015). LOW POWER MULTIPLIER USING BYPASSINGZERO ARCHITECTURE. International Journal of Advance Engineering and Research Development (IJAERD), 2(2), 192–198. Retrieved from https://ijaerd.org/index.php/IJAERD/article/view/521

Issue

Vol. 2 No. 2 (2015): Volume 2 Issue 2, February 2015

Section

Articles