Design and Implementation of Low Power High-Speed 16-bit Arithmetic Units using different Multipliers in Cadence Virtuoso using 45nm technology
Keywords:
Half Adder, Full Adder, Parallel Adders, Multipliers, Array Multiplier, Wallace Multiplier, Baugh-Wooley Multiplier, Vedic Multiplier, AUAbstract
A low power high-speed four Arithmetic Units are designed using different multipliers, each multiplier in
each Arithmetic Unit. This project helps to choose a low power high-speed Arithmetic Unit in designing of different
systems.AU stands for Arithmetic Unit, which is the main functional unit in most digital and high- performance systems
The performance of Arithmetic Unit mainly depends on the performance of multiplier. The speed and area of the
multiplier to be optimized is a major design issue. To determine the best solution for this problem is by comparing AU
with different multipliers. Four different types of multipliers, Array, Wallace, Baugh-Wooley, Vedic multipliers were
designed using half adders and full adders. Power and delay of Arithmetic Unit with different multipliers are compared.
The working of AU using different multipliers helps to frame a better system with less power consumption and high
speed. The entire design is done using CADENCE Tool with a power supply of 1V in GPDK 45nm technology.
