Sophisticated design of low power high speed full adder by using SR-CPL and Transmission Gate logic

Abstract

Adder are the basic building blocks of any computing system.. These Arithmetic operations are widely used in most
digital computer systems. Addition will be the basic component in arithmetic operation and is the base for arithmetic
operations such as multiplication and the basic adder cell can be modified to function as subtractor by adding another xor
gate and can be used for division. Therefore, 1 -bit Full Adder cell is the most important and basic block of an arithmetic unit
of a system. In this paper we analysis the 1-bit full adder using SR-CPL style of full adder design and Transmission gate style
of design