Survey: Design Procedure of VLSI, FPGA & ASIC Life Cycle’s

Authors

  • M.Pranavi Reddy Mtech Student, VLSI System Design, CVR College of engineering, Hyderabad, India
  • M.Harshitha Mtech Student, VLSI System Design, CVR College of engineering, Hyderabad, India
  • Ch.Revathi Mtech Student, VLSI System Design, CVR College of engineering, Hyderabad, India
  • T. Subha Sri Lakshmi Assistant Professor, ECE Department, CVR College of engineering, Hyderabad, India

Keywords:

VLSI, IC, Mosfet, Fpga, Asic, Verilog

Abstract

In real time world VLSI plays a prominent role. The paper presents a survey of VLSI, FPGA & ASIC life
cycles and its design procedure. The present portable electronic devices like smart phones, Laptops etc., are capable of
multi-functional and multi domain application areas. These types of applications are possible due to the Integrated
Circuit (IC) technology and changes in the design takes place in terms of reduction in transistor size, supply voltage,
time to market etc. These types of complex system on Chip (Soc) devices are designed by using Electronic Design
Automation (EDA) tools to meet all nonfunctional IC design constraints. The selection of EDA tool is based on the type
of design analysis, IC design flow, designer domain knowledge, nonfunctional optimization constraints etc. This paper
gives an overview of VLSI, FPGA & ASIC design flow, advantages, applications and few manufacturing companies of
FPGA and ASIC.

Published

2017-11-25

How to Cite

Survey: Design Procedure of VLSI, FPGA & ASIC Life Cycle’s. (2017). International Journal of Advance Engineering and Research Development (IJAERD), 4(11), 1083-1091. https://ijaerd.org/index.php/IJAERD/article/view/5131

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