Design and Implementation of Sub Modules of Successive Approximation Register A/D Converter

Abstract

This paper describes the implementation of a 8-bit 50 MS/s SAR ADC using 180nm TSMC CMOS VLSI
Process in Mentor Graphics. Here main building blocks of SAR ADC lik e comparator, sample and hold, SAR Register
and DAC are implemented. The supply voltage for this SAR ADC is ±1.8 V. The simulation result shows speed of 50 MHz
achieved with input frequency of 1 MHz and power dissipation of 0.2v.