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DOI will be assigned to every published paper at no additional charge. πŸ“’ Call for Papers β€” Volume 13, Issue 10 (October 2026) | Submission Deadline: October 26, 2026 | Rapid peer review: 2–3 days | Impact Factor: 7.37 (SJIF 2026)

Paper Details

📄 IJAERD-OJS-0536

COMPARISON BETWEEN 3 LEVEL AND 5 LEVEL DIODE CLAMPED INVERTER

Author(s):Kunjal Solanki, Krina Talati, Amit Panchal
Institution:P.G Student
Published In:Vol. 2, Issue 3 β€” March 2015
Page No.:114-120
Domain:Engineering
Type:Research Paper
ISSN (Online):2348-4470
ISSN (Print):2348-6406
Abstract

Multilevel began with the three level inverter. Use of conventional two – level pulse width modulation (PWM)inverter provide less distorted current and voltage but at cost of higher switching losses due to high switching frequency.Multilevel inverter is emerging as a viable alternative for high power, medium voltage application. This paper comparestotal harmonics distortion in three level and five level diode clamped multilevel inverter. Diode –clamped three phasetopology is considered for study. A sinusoidal PWM technique is used to control the switches of the inverter. Simulationstudy confirms the reduction in harmonics distortion.

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🕮 How to Cite

Kunjal Solanki, Krina Talati, Amit Panchal, “COMPARISON BETWEEN 3 LEVEL AND 5 LEVEL DIODE CLAMPED INVERTER”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 3, pp. 114-120, March 2015.

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Vol. 13 | Issue 10
October-2026