Design of High Speed MAC (Multiply and Accumulate) Unit Based On “Urdhva Tiryakbhyam Sutra”
| Author(s) | : | Parth Patel |
| Institution | : | PG Student , Department of Electronics and Communication Engineering Gujarat Technological University Ahmedabad, Gujarat, India |
| Published In | : | Vol. 2, Issue 3 — March 2015 |
| Page No. | : | 121-126 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
This paper describes the implementation of a 32x32-bit multiply accumulate (MAC) unit designed using ancientVedic mathematical techniques. This research work presents the efficiency of Urdhva Triyakbhyam Vedic method formultiplication which strikes a difference in actual process of multiplication itself. It enables the parallel generation ofpartial products and eliminates unwanted multiplication and addition steps. Multiply Accumulate unit is a key componentin the most of the digital signal processors, in order to make a balance in the key performance characters such as speed,power and area, a gate level implementation of the design is adopted in the entire research work. An analysis of the bestadder among some commonly available adders is carried out and the best adder is used for adding the partial productgenerated in the Vedic multiplication technique to reduce the combinational delay in the critical path. The proposedresearch work is coded in VHDL, and analysis in-terms of speed power and area is done using Xilinx ISE 14.6 tool.
Parth Patel, “Design of High Speed MAC (Multiply and Accumulate) Unit Based On “Urdhva Tiryakbhyam Sutra””, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 3, pp. 121-126, March 2015.
