Paper Details

This paper presents the design of a novel OCP network to support guaranteed traffic permutation inmultiprocessor SOC applications. The proposed network employs a pipelined circuit-switching approach combined with adynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime patharrangement for arbitrary traffic permutations. The existing system having only fixed priority logic scheme for dynamic pathset up .In this paper we proposed a new PAB based priority logic to rectify the drawbacks in previous arbiter system inproposed OCP network. The PAB contains F-Priority, RR-Priority, D-Priority logics. This circuit-switching approach offersa guarantee of permuted data and its compact overhead enables the benefit of stacking multiple net-works. The proposed onchip network improves the efficiency. Finally implemented the design using Xilinx ISE 12.1 software on FPGA Spartan 3Efamily kit, NEXYS 2 board and showed the synthesis result and power result. The Proposed system OCP network with PABimproves the power, delay and improves the data efficiency.

P.LAKSHMI KANTH, L.S.DEVARAJ, “Improved Data Efficiency of Programmable Arbiter Based On-Chip Permutation Network for MPSOC”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 9, pp. 20-25, September 2015.