Paper Details

Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular,digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as registerfile, Dual Dynamic Flip-Flop Based on a Signal Feed-Through Scheme, and first infest out. A low-power flip-flop (FF)design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signalfeed-through scheme is presented. The proposed design successfully solves the long discharging path problem inconventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Basedon post-layout simulation results using cadence CMOS 180-nm technology, the proposed design outperforms theconventional P-FF design data-close-to-output (MHLFF) by 8.2% in data-to-Q delay. In the meantime, the performanceedges on power and power- delay-product metrics are 24.6% and 31.7%, respectively.

S. KEERTHANA, R. ARIGOVINDAN, J. VASANTHARAJ, “DESIGN OF LOW POWER PULSE TRIGGERED DUAL DYNAMIC FLIP FLOP BASED ON A SIGNAL FEED-THROUGH SCHEME”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 3, Issue 4, pp. 309-315, April 2016.