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DOI will be assigned to every published paper at no additional charge. πŸ“’ Call for Papers β€” Volume 13, Issue 9 (September 2026) | Submission Deadline: September 30, 2026 | Rapid peer review: 2–3 days | Impact Factor: 7.37 (SJIF 2026)

Paper Details

📄 IJAERD-OJS-5591

DESIGN AND IMPLEMENTATION OF SERIAL PERIPHERAL INTERFACE

Author(s):VADLA SIVA PRASAD, Shaik.TAJMAHABOOB
Institution:Student, Dept. of Electrical &Electronics Engineering, JNTUACEP, Pulivendula, A.P., India
Published In:Vol. 5, Issue 4 β€” April 2018
Page No.:2250-2257
Domain:Engineering
Type:Research Paper
ISSN (Online):2348-4470
ISSN (Print):2348-6406
Abstract

SPI stands for Serial Peripheral Interface, A typical processor based system not only has to acquire dataand process it, but also requires secondary devices like sensors, real time clocks, or communication channels to receiveand pass process control information to and from other processors. SPI bus protocol is mainly used for IC to ICcommunication within the system. SPI provides synchronous serial communication between two IC’s. SPI is developedby Motorola for Interfacing micro controllers, microprocessors and various devices such sensors, memory chips,printers, and data converters. SPI architecture consists of one Master and one or more slaves. The aim of the project isto develop SPI master-slave interface in verilog and verify the same using self checking test bench. Verilog standardizedas IEEE 1164, is a Hardware Description Language (HDL). This paper presents a full explanation of a SerialPeripheral Interface bus protocol. The SPI Master and Slave can be designed and implemented on Spartan FPGA kitand results can be simulated using Xilinx ISE 12.4 simulator.

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🕮 How to Cite

VADLA SIVA PRASAD, Shaik.TAJMAHABOOB, “DESIGN AND IMPLEMENTATION OF SERIAL PERIPHERAL INTERFACE”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 4, pp. 2250-2257, April 2018.

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Vol. 13 | Issue 9
September 2026