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DOI will be assigned to every published paper at no additional charge. 📢 Call for Papers — Volume 13, Issue 9 (September 2026) | Submission Deadline: September 30, 2026 | Rapid peer review: 2–3 days | Impact Factor: 7.37 (SJIF 2026)

Paper Details

📄 IJAERD-OJS-5702

Implementation of Three Phase 12-Step VSI with Harmonics Reduction

Author(s):Mayur H. Maheswari, Madhusudan V. Gohil, Mayuri tahilramani
Institution:Electrical department, Dr. Jivraj Mehta Institute of Technology, Mogar, Gujarat
Published In:Vol. 2, Issue 13 — January 2015
Page No.:-
Domain:Engineering
Type:Research Paper
ISSN (Online):2348-4470
ISSN (Print):2348-6406
Abstract

In this paper a novel circuit topology forreducing the harmonics in the output voltage of a three-phasevoltage-source inverter is proposed. It is found that incomparison with conventional conduction modes like 120°and 180°, there are introduced less harmonics with 150°conduction mode. The quality of output voltage can beimproved by only changing the conduction mode which isvery simple to implement. In this paper, the scheme isimplemented and tested for 1.5kW, 50 Hz VSI. The controlsignals are generated using AT89C51 microcontroller. Theoutput waveforms under various load conditions wereexamined, analyzed and verified.

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🕮 How to Cite

Mayur H. Maheswari, Madhusudan V. Gohil, Mayuri tahilramani, “Implementation of Three Phase 12-Step VSI with Harmonics Reduction”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 13, pp. -, January 2015.

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