NOVEL ENERGY EFFICIENT CARRY SKIP ADDER BASED ON DUAL MODE LOGIC DESIGN
| Author(s) | : | Ms.C.Aishwarya, Mrs.J.R.Beny, R. Rajasekaran, G.Abirami |
| Institution | : | Department of EEE, SNS College of Technology, Coimbatore |
| Published In | : | Vol. 5, Issue 14 — January 2018 |
| Page No. | : | - |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
The dual mode logic (DML) gates family proposed here empowers a very high level of energy-delayoptimization flexibility at the very gate level. In this paper, this adaptability is utilized to enhance energy efficiency andperformance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates thedesign's critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths operatein the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumptionreduction. The proposed approach is analyzed on a 128 bit carry skip adder.
Ms.C.Aishwarya, Mrs.J.R.Beny, R. Rajasekaran, G.Abirami, “NOVEL ENERGY EFFICIENT CARRY SKIP ADDER BASED ON DUAL MODE LOGIC DESIGN”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 14, pp. -, January 2018.
